With the progress of the miniaturization of semiconductor devices, the leakage current caused by shorting across bit and word lines ascribable e.g. to crossing failure is becoming non-negligible. In a semiconductor storage device of these days, a redundancy circuit for remedying a malfunctioning cell is provided, such that a fail cell, suffering from crossing failure, can be replaced by a redundant cell. However, even if such a fail cell is relieved by the redundant cell, a current path produced by shorting across the bit and word lines is left unremedied, so that power dissipation ascribable to the leakage current poses a problem. In particular, in a low power type semiconductor storage device, having the low power operation mode, also termed a power-down or standby mode, such leakage current leads to increased standby current.
Up to now, various proposals have been made as a countermeasure against crossing failure caused by the leakage current across the bit and word lines. As a representative technique for reducing the leakage current, caused by shorting across the bit and word lines, there is known a configuration in which a high-resistance transistor (transistor having a long channel length), a diode or a high-resistance conductor is inserted across a bit line precharge potential and the bit lines, by way of limiting the current.
A few of publications of the relevant art are now explained. As typical of the semiconductor storage device, designed to reduce the leakage current across the bit and word lines, ascribable to crossing failure, the configuration shown for example in FIG. 11 has been proposed (see Patent Document 1, indicated hereinbelow). Referring to FIG. 11, a bit line precharge current limiter PT1 is provided in a bit line precharge equalizing circuit 214 in order to minimize the current flow on occurrence of crossing failure, by way of limiting the bit line current. In FIG. 11, transistors TN2 and TN3, each having a gate connected to a precharge equalizing line PEQ, represent a circuit for precharging bit lines BL and /BL, connected to the sources of the transistors, to a precharge potential. An over-bar on BL in the drawing is depicted herein by a slash mark (/). The drains of the transistors are connected in common and connected via transistor TN4 to an output of a precharge power supply circuit 210. A transistor TN1, having a gate connected to PEQ, is an equalizing circuit for balancing the bit lines BL and /BL.
There is also known a DRAM in which a bit line precharging circuit is provided with an active current limiter for selectively limiting the amount of the precharge current, under control by the ternary-valued voltage supplied from the column selection line, and in which the current path during the chip standby time may be interrupted even on occurrence of shorting across the bit and word lines (see Patent Document 2, indicated hereinbelow). This Patent Document 2 discloses such a configuration in which a precharge transistor is connected to a precharge potential equal to ½ VCC via a depletion NMOS transistor, and in which a negative voltage is supplied from an associated column selection line to the gate of the depletion type NMOS transistor to interrupt the current path.
There is also known a configuration of a semiconductor storage device in which the standby current is not increased by a bit line having a path for the leakage current, with the bit line not being in the floating state during the standby period. In this configuration, there is provided a potential setting means connected to each bit line for fixing the potential of the bit line to the potential of the destination of the path for the leakage current. For a normal sub-array, the totality of the bit lines of the sub-array is pre-charged to a preset potential by a precharging means. For a sub-array having a path for the leakage current, precharging is not carried out during the standby period by the precharging means, with the potential setting means being in the operative state. The potential setting means is formed by a dummy memory cell for setting a potential at a bit line holding potential (see for example the Patent Document 3, indicated hereinbelow).
There is also known a configuration in which, in transferring to the standby (power-down) state, responsive to a chip select signal, the bit line is transiently set to a floating state, the potential on the bit line at such time is held in a latch circuit, it is then determined, in dependence upon the potential, whether or not the bit line is to be coupled to the power supply potential, and in which the bit line is disconnected from the power supply potential on occurrence of a minor shorting on the bit line to decrease the standby current (for example, see the Patent Document 4, indicated below).